#define VSPW 5 
#define VBPD 16
#define VFPD 50
#define HSPW 2	
#define HBPD 44
#define HFPD 46 
#define HDP 720  
#define VDP 720
//////////////NV3052CGRB+BOE4.0////////////
Wrt_Reg_3052(0xFF,0x30);
Wrt_Reg_3052(0xFF,0x52);
Wrt_Reg_3052(0xFF,0x01);
Wrt_Reg_3052(0xE3,0x00);
Wrt_Reg_3052(0x0A,0x11);
Wrt_Reg_3052(0x23,0xA0);//A2
Wrt_Reg_3052(0x24,0x32);
Wrt_Reg_3052(0x25,0x12);
Wrt_Reg_3052(0x26,0x2E);
Wrt_Reg_3052(0x27,0x2E);

Wrt_Reg_3052(0x29,0x02);
Wrt_Reg_3052(0x2A,0xCF);
Wrt_Reg_3052(0x32,0x34);
Wrt_Reg_3052(0x38,0x9C);
Wrt_Reg_3052(0x39,0xA7);
Wrt_Reg_3052(0x3A,0x27); 
Wrt_Reg_3052(0x3B,0x94);
Wrt_Reg_3052(0x42,0x6D);
Wrt_Reg_3052(0x43,0x83);
Wrt_Reg_3052(0x81,0x00);
Wrt_Reg_3052(0x91,0x67);
Wrt_Reg_3052(0x92,0x67);
Wrt_Reg_3052(0xA0,0x52);
Wrt_Reg_3052(0xA1,0x50);
Wrt_Reg_3052(0xA4,0x9C);
Wrt_Reg_3052(0xA7,0x02);
Wrt_Reg_3052(0xA8,0x02);
Wrt_Reg_3052(0xA9,0x02);
Wrt_Reg_3052(0xAA,0xA8);
Wrt_Reg_3052(0xAB,0x28);
Wrt_Reg_3052(0xAE,0xD2);
Wrt_Reg_3052(0xAF,0x02);
Wrt_Reg_3052(0xB0,0xD2);
Wrt_Reg_3052(0xB2,0x26);
Wrt_Reg_3052(0xB3,0x26);
Wrt_Reg_3052(0xFF,0x30);
Wrt_Reg_3052(0xFF,0x52);
Wrt_Reg_3052(0xFF,0x02);
Wrt_Reg_3052(0xB1,0x0A);
Wrt_Reg_3052(0xD1,0x0E);
Wrt_Reg_3052(0xB4,0x2F);
Wrt_Reg_3052(0xD4,0x2D);
Wrt_Reg_3052(0xB2,0x0C);
Wrt_Reg_3052(0xD2,0x0C);
Wrt_Reg_3052(0xB3,0x30);
Wrt_Reg_3052(0xD3,0x2A);
Wrt_Reg_3052(0xB6,0x1E);
Wrt_Reg_3052(0xD6,0x16);
Wrt_Reg_3052(0xB7,0x3B);
Wrt_Reg_3052(0xD7,0x35);
Wrt_Reg_3052(0xC1,0x08);
Wrt_Reg_3052(0xE1,0x08);
Wrt_Reg_3052(0xB8,0x0D);
Wrt_Reg_3052(0xD8,0x0D);
Wrt_Reg_3052(0xB9,0x05);
Wrt_Reg_3052(0xD9,0x05);
Wrt_Reg_3052(0xBD,0x15);
Wrt_Reg_3052(0xDD,0x15);
Wrt_Reg_3052(0xBC,0x13);
Wrt_Reg_3052(0xDC,0x13);
Wrt_Reg_3052(0xBB,0x12);
Wrt_Reg_3052(0xDB,0x10);
Wrt_Reg_3052(0xBA,0x11);
Wrt_Reg_3052(0xDA,0x11);
Wrt_Reg_3052(0xBE,0x17);
Wrt_Reg_3052(0xDE,0x17);
Wrt_Reg_3052(0xBF,0x0F);
Wrt_Reg_3052(0xDF,0x0F);
Wrt_Reg_3052(0xC0,0x16);
Wrt_Reg_3052(0xE0,0x16);
Wrt_Reg_3052(0xB5,0x2E);
Wrt_Reg_3052(0xD5,0x3F);
Wrt_Reg_3052(0xB0,0x03);
Wrt_Reg_3052(0xD0,0x02);
Wrt_Reg_3052(0xFF,0x30);
Wrt_Reg_3052(0xFF,0x52);
Wrt_Reg_3052(0xFF,0x03);
Wrt_Reg_3052(0x08,0x09);		
Wrt_Reg_3052(0x09,0x0A);		
Wrt_Reg_3052(0x0A,0x0B);		
Wrt_Reg_3052(0x0B,0x0C);		
Wrt_Reg_3052(0x28,0x22);		
Wrt_Reg_3052(0x2A,0xE9);	
Wrt_Reg_3052(0x2B,0xE9);							  				  
Wrt_Reg_3052(0x34,0x51);
Wrt_Reg_3052(0x35,0x01);
Wrt_Reg_3052(0x36,0x26);  
Wrt_Reg_3052(0x37,0x13);
Wrt_Reg_3052(0x40,0x07);  
Wrt_Reg_3052(0x41,0x08);  
Wrt_Reg_3052(0x42,0x09);  
Wrt_Reg_3052(0x43,0x0A);
Wrt_Reg_3052(0x44,0x22);
Wrt_Reg_3052(0x45,0xDB);  
Wrt_Reg_3052(0x46,0xdC);  
Wrt_Reg_3052(0x47,0x22);
Wrt_Reg_3052(0x48,0xDD);  
Wrt_Reg_3052(0x49,0xDE); 
Wrt_Reg_3052(0x50,0x0B);  
Wrt_Reg_3052(0x51,0x0C);  
Wrt_Reg_3052(0x52,0x0D);  
Wrt_Reg_3052(0x53,0x0E); 
Wrt_Reg_3052(0x54,0x22);
Wrt_Reg_3052(0x55,0xDF);  
Wrt_Reg_3052(0x56,0xE0);  
Wrt_Reg_3052(0x57,0x22);
Wrt_Reg_3052(0x58,0xE1);  
Wrt_Reg_3052(0x59,0xE2); 
Wrt_Reg_3052(0x80,0x1E);   
Wrt_Reg_3052(0x81,0x1E);   
Wrt_Reg_3052(0x82,0x1F);   
Wrt_Reg_3052(0x83,0x1F);   
Wrt_Reg_3052(0x84,0x05);   
Wrt_Reg_3052(0x85,0x0A);   
Wrt_Reg_3052(0x86,0x0A);   
Wrt_Reg_3052(0x87,0x0C);   
Wrt_Reg_3052(0x88,0x0C);   
Wrt_Reg_3052(0x89,0x0E);   
Wrt_Reg_3052(0x8A,0x0E);    
Wrt_Reg_3052(0x8B,0x10);   
Wrt_Reg_3052(0x8C,0x10);    
Wrt_Reg_3052(0x8D,0x00);   
Wrt_Reg_3052(0x8E,0x00);   
Wrt_Reg_3052(0x8F,0x1F);   
Wrt_Reg_3052(0x90,0x1F);   
Wrt_Reg_3052(0x91,0x1E);   
Wrt_Reg_3052(0x92,0x1E);      
Wrt_Reg_3052(0x93,0x02);   
Wrt_Reg_3052(0x94,0x04); 
Wrt_Reg_3052(0x96,0x1E);   
Wrt_Reg_3052(0x97,0x1E);   
Wrt_Reg_3052(0x98,0x1F);   
Wrt_Reg_3052(0x99,0x1F);   
Wrt_Reg_3052(0x9A,0x05);   
Wrt_Reg_3052(0x9B,0x09);   
Wrt_Reg_3052(0x9C,0x09);   
Wrt_Reg_3052(0x9D,0x0B);   
Wrt_Reg_3052(0x9E,0x0B);   
Wrt_Reg_3052(0x9F,0x0D);   
Wrt_Reg_3052(0xA0,0x0D);   
Wrt_Reg_3052(0xA1,0x0F);   
Wrt_Reg_3052(0xA2,0x0F);   
Wrt_Reg_3052(0xA3,0x00);   
Wrt_Reg_3052(0xA4,0x00);   
Wrt_Reg_3052(0xA5,0x1F);   
Wrt_Reg_3052(0xA6,0x1F);   
Wrt_Reg_3052(0xA7,0x1E);   
Wrt_Reg_3052(0xA8,0x1E);   
Wrt_Reg_3052(0xA9,0x01);   
Wrt_Reg_3052(0xAA,0x03);  
 
Wrt_Reg_3052(0xFF,0x30);
Wrt_Reg_3052(0xFF,0x52);
Wrt_Reg_3052(0xFF,0x00);
Wrt_Reg_3052(0x36,0x0A);             
Wrt_Reg_3052(0x11,0x00);
Delay_ms(200); 
Wrt_Reg_3052(0x29,0x00);
Delay_ms(100);